Big data flow processing
Tasks up-scalability keeping constant latency
FPGAs implementation speeds up development of prototypes significantly and makes it smooth to switch to ASIC production due to integrated tools for fast scaling of device manufacturing
The average data processing speed reached using Altera Stratix IV is over 2000 Mbps for random data and over 3100 Mbps for typical customer data blocks.
The system is implemented in Verilog language. Debugging was performed on the STRATIX-IV family FPGA from Altera, the target platform was a specialized ASIC.
FPGA carries out modulation and demodulation of signals at an intermediate frequency with the possibility of software algorithm changes, error correction, data transfer to the controller, modem parameter management. NIOS II provides control of the modem parameters and the formation of control signals (interfaces I2C, SPI) for the circuits of the receiving / transmitting path.
Device is connected to control host via SRIO interface. When commanded from the host, the specified number of ADC data samples is copied to the DDR memory area, is filtered, and then this data is transferred via SRIO 4-channel sequential interface.
Device based on FPGA Cyclone II and STM32 microcontroller. ADC with 40 MHz sampling rate. Signal filtering, base line correction, superimposed pulse rejection is performed in FPGA. The amplitude spectrum is stored in the FPGA internal RAM and transferred on request to the microcontroller, where secondary processing is performed.
The firmware is developed: high-level part (data conversion) is written in SystemC, low-level part (implementation of interface protocols) – in VHDL. Implemented:
The customer program is executed in the ARM core of the same FPGA.