FPGA design
FPGA is the best option for the following tasks
- Hard Real Time - deterministic behavior and guaranteed task execution timeframes
- The least latency in compare with any other solution
Additional features
Big data flow processing
High performance
Tasks up-scalability keeping constant latency
FPGAs implementation speeds up development of prototypes significantly and makes it smooth to switch to ASIC production due to integrated tools for fast scaling of device manufacturing
Application areas
- Autonomous vehicles, robotics, industrial manufacturing
- Big dataflow preprocessing for NN inference executed by MPU
Our FPGA background
The average data processing speed reached using Altera Stratix IV is over 2000 Mbps for random data and over 3100 Mbps for typical customer data blocks.
The system is implemented in Verilog language. Debugging was performed on the STRATIX-IV family FPGA from Altera, the target platform was a specialized ASIC.
FPGA carries out modulation and demodulation of signals at an intermediate frequency with the possibility of software algorithm changes, error correction, data transfer to the controller, modem parameter management. NIOS II provides control of the modem parameters and the formation of control signals (interfaces I2C, SPI) for the circuits of the receiving / transmitting path.
Device is connected to control host via SRIO interface. When commanded from the host, the specified number of ADC data samples is copied to the DDR memory area, is filtered, and then this data is transferred via SRIO 4-channel sequential interface.
Device based on FPGA Cyclone II and STM32 microcontroller. ADC with 40 MHz sampling rate. Signal filtering, base line correction, superimposed pulse rejection is performed in FPGA. The amplitude spectrum is stored in the FPGA internal RAM and transferred on request to the microcontroller, where secondary processing is performed.
The firmware is developed: high-level part (data conversion) is written in SystemC, low-level part (implementation of interface protocols) – in VHDL. Implemented:
- modes of single-sided and double-sided printing;
- the ability to print at higher speeds with lower resolution (because at higher speeds, there is not enough bandwidth available buses);
- software for modeling and quick adaptation of the system for printheads of different configurations.
The customer program is executed in the ARM core of the same FPGA.
IP-cores
I/Q input data corrector
Recovery of I/Q constant component.
Signal detection and amplitude self-tuning block
Determines input signal occurrence by overcoming specified power limit, automatically causes the amplitude to coincide with specified value.
Band pass filter
Selects bandwidth according to received signal.
Frequency demodulator
Converts modulated FSK to bitstream.
Phase demodulator
Converts modulated PSK, QPSK to bitstream
Character synchronization block
Dates capture of bit value, forms character symbols array.
Frequency modulator
Modulates FSK signal.
Phase modulator
Modulates PSK, QPSK signal.
Raised-cosine filter for PSK, QPSK transceiver
Narrows spectrum of Frequency modulated signal.
Gaussian filter for FSK transceiver
Narrows spectrum of Frequency modulated signal.
Fourier transformation
Air analysis, determining jamming and unjammed channels.
Interface blocks
UART, SPI, I2C
System-On-Chip
Manages transceiver and can take additional functions (if required). Based on ARM processors (hardware or FPGA-simulated).
Frequency translation block
Translates signal frequency to higher or lower interval.